부산대학교 도서관

Degradation mechanisms, such as Bias Temperature Instabilities (BTI) and Hot Carrier Degradation (HCD), as well as the associated time-dependent variability, dictate the limit on the acceptable operating voltage conditions in modern deeply-scaled VLSI devices. Based on large statistical datasets, acquired using specifically designed on-chip arrays, we experimentally obtain DC degradation maps for both $\boldsymbol{n}$ - and $\boldsymbol{p}$-type FETs. Defect-centric based analysis of the statistical parameters at every $\boldsymbol{V_{G}}, \boldsymbol{V_{D}}$ bias point provides physical insights in the underlying single- and multi-carrier degradation processes. As a result, we can separate the defect charging contributions of each degradation mechanism and describe to which extent these mechanisms co-interact. We finally present a simplified model (the “3-bucket” model) that is able to describe the degradation statistics up to $3\boldsymbol{\sigma}$ of a device population subject to an arbitrary combination of BTI and HCD stress.