부산대학교 도서관

This paper describes a 66 MHz 2.3 M Content Addressable Memory (CAM) which uses DRAM technology for the basic ternary CAM cell. The chip's architecture allows a high speed search operation and single cycle learning. The DRAM based cell structure enables implementation of a larger table size than is available in similar technology SRAM based CAMs. A new matchline sense amplifier allows fast, low power sensing of the matchline. Among the chip's many features are a DDR input interface and the ability to cascade up to eight parts without additional logic. The density and speed of this part make it suitable for many applications such as network switching.