학술논문
3.3 A 5GS/s 158.6mW 12b Passive-Sampling 8×-Interleaved Hybrid ADC with 9.4 ENOB and 160.5dB FoMS in 28nm CMOS
Document Type
Conference
Author
Source
2019 IEEE International Solid-State Circuits Conference - (ISSCC) Solid-State Circuits Conference - (ISSCC), 2019 IEEE International. :62-64 Feb, 2019
Subject
Language
ISSN
2376-8606
Abstract
Emerging 5G communication systems require ADCs to directly digitize wide bandwidth (BW) signals with high spectral purity at low power consumption. Current state-of-the-art solutions include mainly time-interleaved (TI) pipelined [1–4] or pipelined-SAR [5] architectures, enhanced by digital calibration. To ensure a sufficiently high input BW, all these designs employ a static front-end buffer. This buffer often dissipates more power than the ADC itself, significantly deteriorates the linearity and noise performance, and severely limits the available swing, unless over-voltage or multiple supplies are used [1–5].