학술논문

Ru Liner Scaling with ALD TaN Barrier Process for Low Resistance 7 nm Cu Interconnects and Beyond
Document Type
Conference
Source
2018 IEEE International Interconnect Technology Conference (IITC) Interconnect Technology Conference (IITC), 2018 IEEE International. :40-42 Jun, 2018
Subject
Communication, Networking and Broadcast Technologies
Signal Processing and Analysis
Resistance
Conductivity
Electrical resistance measurement
Metals
Plating
Temperature measurement
Inspection
Cu
CVD Ru
ALD TaN
low resistance
7nm
Language
ISSN
2380-6338
Abstract
Low resistance Cu interconnects with CVD Ru liner have been demonstrated for 7 nm node. Ru liner thickness reduction has been achieved by replacing PVD TaN with a bilayer PVD Ta and ALD TaN stack, while maintaining adequate Cu fill performance. The newly proposed barrier stack (PVD Ta/AldTaN) with thin Ru liner studied in this paper also enabled a significant Ru CMP performance improvement by mitigating two major Ru CMP issues: Cu recess of narrow lines, and trench height variability between dense and isolated patterns. Furthermore, this novel barrier stack with Ru liner could attain void-free Cu fill even for beyond 7 nm node dimension. Thus, the PVD Ta/ALD TaN/CVD Ru liner is a promising candidate as the liner for Cu interconnects of 7 nm node and beyond.