부산대학교 도서관

In the era of IoT, everything is connected through mutual data communication. System designers keep raising the bar for faster data transmission speed and wider data bandwidth to meet the ever-increasing data transmission demands from clouds computing such as data centers, servers, AI to edge devices such as mobile devices, AR/VRs, cars, robots, drone and so on. To resolve aforementioned huge data growth challenges, the next-generation advanced packaging solutions in 5G and RF mmWave communication become a very hot research topic among semiconductor industry as well as academic community. Particularly, how to provide a high density, high speed interconnect link with a minimized electrical transmission loss at high frequency becomes a critical R&D subject for packaging designers. In this paper, we demonstrated the first time a fine pitch, two-layers embedded Cu dual damascene RDLs with stacked vias on a 300 mm wafer using a single lithography dielectrics film. Each RDL layer composes of a sub-5 µm microvias and a 2 µm/1 µm line/ space (L/S) escape routing using a Cu dual damascene process. A liquid photoimageable dielectrics film was used for the fabrication of microvias and RDL trenches using a UV lithography tool. To achieve a good total thickness variation (TTV) control within the thin dielectrics film, a CMP process was applied to remove the plated Cu overburden and seed metal from the dielectrics surface while maintaining a smooth planarization surface to minimize the electrical transmission loss when system chips running at a high frequency. With demonstrated fine pitch, multi-layers Cu dual damascene RDLs, the existing wafer level fan-out SiP technologies can be readily extended to realize the next-generation high density, high performance advanced packaging in 5G and RF mmWave applications.