학술논문

A 36.4dB SNDR @ 5GHz 1.25GS/s 7b 3.56mW single-channel SAR ADC in 28nm bulk CMOS
Document Type
Conference
Source
ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference. :167-170 Sep, 2017
Subject
Bioengineering
Communication, Networking and Broadcast Technologies
General Topics for Engineers
Power, Energy and Industry Applications
Signal Processing and Analysis
Switches
Linearity
Switching circuits
Complexity theory
Delays
Capacitance
Successive approximation register
high sampling rate
high bandwidth
low power
bootstrapped input switch
capacitive DAC (CDAC)
dynamic comparator
Language
Abstract
A 1.25GS/s 7b single-channel SAR ADC is presented with an SNDR/SFDR of 41.4dB/51dB at low frequencies, while the SNDR/SFDR at Nyquist are 40.1dB/52dB and remain still 36.4dB/50.1dB at 5GHz. The high input frequency linearity is enabled by a fast bootstrap circuit for the input switch, while the high sampling rate, the highest among recently published >34dB SNDR single-channel SAR ADCs is achieved by a Triple-Tail dynamic comparator and a Unit-Switch-Plus-Cap (USPC) DAC. The prototype ADC in 28nm CMOS consumes only 3.56mW from a 1V supply, leading to a Walden FoM of 34.4fJ/conv-step at Nyquist for a core chip area of 0.0071mm 2 .