학술논문
The CHESS-2 prototype in AMS 0.35 μm process: A high voltage CMOS monolithic sensor for ATLAS upgrade
Document Type
Conference
Author
Tamma, C.; Caragiulo, P.; Grabas, H.; Xu, X.; Markovic, B.; Segal, J.; Dragone, A.; Kenney, C.; Su, D.; Grenier, P.; Fadeyev, V.; Grillo, A. A.; Haller, G.; Affolder, A.; Arndt, K.; Bates, R.; Benoit, M.; Di Bello, F.; Blue, A.; Bortoletto, D.; Buckland, M.; Buttar, C.; Das, D.; Dopke, J.; Ehrler, F.; Galloway, Z.; Gregor, I. M.; Hiti, B.; Hoeferkamp, M.; Hommels, L. B. A.; Huffman, T.; John, J.; Kanisauskas, K.; Kramberger, G.; Liang, Z.; Mandic, I.; Maneuski, D.; Martinez-Mckinney, F.; McMahon, S.; Meng, L.; Mikuz, M.; Muenstermann, D.; Nickerson, R.; Peric, I.; Phillips, P.; Plackett, R.; Rubbo, F.; Seidel, S.; Seiden, A.; Shipsey, I.; Song, W.; Stanitzki, M.; Turchetta, R.; Vigani, L.; Volk, J.; Wang, R.; Warren, M.; Wilson, F.; Worm, S.; Xiu, Q.; Zhang, J.; Zhu, H.
Source
2016 IEEE Nuclear Science Symposium, Medical Imaging Conference and Room-Temperature Semiconductor Detector Workshop (NSS/MIC/RTSD) Nuclear Science Symposium, Medical Imaging Conference and Room-Temperature Semiconductor Detector Workshop (NSS/MIC/RTSD), 2016. :1-5 Oct, 2016
Subject
Language
Abstract
CHESS-2 (CMOS HV Evaluation for Strip Sensors) is a novel ASIC strip architecture designed to investigate the feasibility of using HV-CMOS MAPS (Monolithic Active Pixel Sensors) as alternative sensors for the ATLAS Phase-II Strip Tracker Upgrade. The ASIC is optimized for signal processing, hit pixel position encoding and readout. CHESS-2 includes three independent groups of 128 strips composed of 32 pixels each. The pixel includes a charge sensitive amplifier and the first stage of a comparator inside the collecting well. The second stage, the configuration, the encoding and the readout sections are placed at the periphery of the strips. A novel “fast skip” hit encoding logic identifies the first 8 hit pixel positions with a single-bunch time resolution (25 ns) and sends the data to a fast readout circuitry for serialization and transmission on 14 LVDS channels at 320 MHz. Several substrate resistivity variants have been fabricated for a full characterization of the performance aspects.