학술논문
Resistive Address Decoder
Document Type
Periodical
Author
Source
IEEE Computer Architecture Letters IEEE Comput. Arch. Lett. Computer Architecture Letters. 16(2):141-144 Dec, 2017
Subject
Language
ISSN
1556-6056
1556-6064
2473-2575
1556-6064
2473-2575
Abstract
Hardwired dynamic NAND address decoders are widely used in random access memories to decode parts of the address. Replacing wires by resistive elements allows storing and reprogramming the addresses and matching them to an input address. The resistive address decoder thus becomes a content addressable memory, while the read latency and dynamic energy remain almost identical to those of a hardwired address decoder. One application of the resistive address decoder is a fully associative TLB with read latency and energy consumption similar to those of a one-way associative TLB. Another application is a many-way associative cache with read latency and energy consumption similar to those of a direct mapped one. A third application is elimination of physical addressing and using virtual addresses throughout the entire memory hierarchy by introducing the resistive address decoder into the main memory.