학술논문
Architecture of a parallel computer Cenju-4
Document Type
Conference
Author
Source
Innovative Architecture for Future Generation High-Performance Processors and Systems Architecture for future generation high-performance processors and systems Innovative Architecture for Future Generation High-Performance Processors and Systems, 1998. :105-113 1998
Subject
Language
ISSN
1537-3223
Abstract
This paper describes the architecture and the evaluation results of a parallel computer Cenju-4. Cenju-4 supports two memory architectures: distributed memory with user-level message passing communication and distributed shared memory with cache-coherent nonuniform memory access (cc-NUMA) feature. Cenju-4 system consists of from 8 to 1024 nodes connected by a multistage network which has multicast, synchronization, and gather functions. Cenju-4 adopts a Mach micro kernel based operating system, which provides several services for parallel processing. We attained 5.5 psec communication latency and 168 Mbytes/sec communication throughput an message passing communication.