부산대학교 도서관

Electronic power systems follow the general trend of miniaturization and functional density. 3D technologies provide an interesting response if adapted to power specifications. In the framework of the ENIAC JU funded project Enhanced Power Pilot Line (EPPL), a new type of device has been proposed consisting of an H bridge of power transistors and a Si interposer. This paper presents an H bridge of four power MOS transistors (DMOS) assembled to a through silicon via (TSV) last passive silicon (Si) interposer. The full conception to meet power specifications of 10A and 600W is reported from the interposer design strategy to the integration process flow and mounting operations in a 200mm fabrication line. Morphological characterization shows a successful integration of the DMOS transistor to the silicon interposer. Moreover, electrical characterizations of various types of interconnection chains highlight the possibilities of the rerouting scheme inside the interposer. The good electrical performance of the setup is reflected for example in the very low Kelvin TSV contact resistance of 2.1mΩ as well as by fully functional DMOS devices.