학술논문
A 125 mW 8.5–11.5 Gb/s serial link transceiver with a dual path 6-bit ADC/5-tap DFE receiver and a 4-tap FFE transmitter in 28 nm CMOS
Document Type
Conference
Author
Source
2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) VLSI Circuits (VLSI-Circuits), 2016 IEEE Symposium on. :1-2 Jun, 2016
Subject
Language
Abstract
This paper describes an 8.5–11.5 Gb/s transceiver with a dual path receiver and a voltage-mode transmitter. The RX can operate either in ADC mode for complex loss channels such as optical multimode fiber or in DFE mode for copper-based backplane links. The ADC path implements a 2X interleaved 6-bit rectifying flash ADC using a programmable gain amplifier (PGA) with controlled bandwidth and peaking, comparator pipelining, and super-source follower circuit techniques. The LRM optical sensitivity requirements are met with a > 6 dB margin while achieving an ENOB of 4.59 bits at a 5 GHz input frequency. The TX/RX DFE path achieves copper channel loss compensation of 38 dB with BER < 10 −12 at 11.5 Gb/s consuming 46mW from a 0.9V supply. The TX/RX ADC path consumes 125 mW at 10.3125 Gb/s. The TX/RX occupies 0.56 mm 2 in a 28nm standard CMOS process.