학술논문

High power gain low noise amplifier design for next generation 1–7GHz wideband RF frontend RFIC using 0.18μm CMOS
Document Type
Conference
Source
2015 19th International Symposium on VLSI Design and Test VLSI Design and Test (VDAT), 2015 19th International Symposium on. :1-5 Jun, 2015
Subject
Components, Circuits, Devices and Systems
Computing and Processing
Signal Processing and Analysis
Wideband
Noise
CMOS integrated circuits
Impedance matching
Radio frequency
Topology
CMOS
LNA
Next Generation
RFIC
Language
Abstract
Next generation wireless terminal should support multiple standards (mobile: GSM, UMTS, WiMAX, LTE etc.; LAN: IEEE 802.11a/b/g etc.; PAN: ZigBee, Bluetooth etc.), receive multiple frequency bands, and allow any modulation scheme. So, Next generation RF (Radio Frequency) Frontend requires wideband with multiple standards support. RF Frontend relaxes tough requirements (dynamic range, speed, noise performance and linearity) of Baseband A/D converter. An LNA (Low Noise Amplifier) of RF Frontend relaxes the noise performance and dynamic range requirements by amplifying weak received signal with adding minimum noise to improve signal to noise ratio. This paper presents a novel hybrid topology low-noise amplifier (LNA) design for wideband receivers and microwave access covering the frequency range from 1 to 7 GHz using 0.18-μm CMOS. Simulation results shows that the power gain reaches a peak of 30 dB in-band with an upper 3dB frequency of 7 GHz with minimum noise figure (NF) 4dB over the band of interest. Input matching is less than −10dB in interested band and the LNA consumes 24mW power at 1.2V supply voltage. A figure of merit is used to compare the proposed design with recently published wideband CMOS LNAs. It shows that the design of LNA achieves comparable good performances. Authors have simulated design using TSMC 0.18μm CMOS technology.