학술논문
Boosting multi-socket cache-coherency with low-latency silicon photonic interconnects
Document Type
Conference
Source
2015 International Conference on Computing, Networking and Communications (ICNC) Computing, Networking and Communications (ICNC), 2015 International Conference on. :830-836 Feb, 2015
Subject
Language
Abstract
Speed-up in computing systems today is most often accomplished by increasing parallelism in both hardware and software. Parallel applications residing wholly on a single multi-core chip generally utilize implicit inter-thread communication via shared memory managed by cache-coherency mechanisms. However, increasing parallelism by creating coherent domains across many chips poses new challenges. In this work, we illustrate the sensitivity of various applications on a theoretical four-socket system to the latency of their coherency traffic, and show that current solutions, such as Quick Path Interconnect (QPI) and HyperTransport (HT), could benefit greatly from a lower latency communication medium. Then, we propose a silicon photonic inter-chip network that achieves very low-latency and falls within a reasonable power budget.