학술논문
22nm technology yield optimization using multivariate 3D virtual fabrication
Document Type
Conference
Author
Source
2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) Simulation of Semiconductor Processes and Devices (SISPAD), 2013 International Conference on. :97-100 Sep, 2013
Subject
Language
ISSN
1946-1569
1946-1577
1946-1577
Abstract
We present a technology development methodology that relies on 3D virtual fabrication to rapidly improve yield by increasing tolerance to multilevel process variation. This methodology has been successfully implemented in the development and yield ramp of high-performance 22nm SOI CMOS technology. Based on virtual metrology, dedicated testsite structures were designed and implemented, with electrical results corroborating virtual findings, validating the methodology. This 3D virtual fabrication technique was used to implement a delicate process change, and the same testsite structures validated the improved process window yield.