학술논문

Multifunction RNS modulo (2n±1) multipliers based on modified booth encoding
Document Type
Conference
Source
2012 IEEE Asia Pacific Conference on Circuits and Systems Circuits and Systems (APCCAS), 2012 IEEE Asia Pacific Conference on. :515-518 Dec, 2012
Subject
Components, Circuits, Devices and Systems
Communication, Networking and Broadcast Technologies
Computing and Processing
Signal Processing and Analysis
Hardware
Adders
Delay
Very large scale integration
Encoding
Finite impulse response filter
Residue number system (RNS)
computer arithmetic
very large scale integration (VLSI) design
Language
Abstract
In this paper, multifunction RNS modulo (2 n ±1) multipliers are proposed. By adopting common circuits for summing up the partial products with extra controls, our proposed multipliers could perform both modulo (2n+1) and (2 n −1) multiplications which is based on Modified Booth Encoding. The proposed multifunction modulo (2 n ±1) multipliers can save more area under the same delay constraints and ADP (Area×Delay Product) compared with the one which only perform the two modulo (2 n +1) and modulo (2 n −1) multiplication operations using the original circuits. Our proposed multipliers could be used to perform successive modulo multiplications on the same hardware.