부산대학교 도서관

Two key C4 reliability concerns for the current and next generation integrated circuits are electromigration (EM) and “white C4” bumps caused by the stresses induced by die-package interactions. This paper discusses novel design and integration changes in the final polymeric passivation via (FV) in order to mitigate white bump and chip-package interaction (CPI) stresses in the ultra-low k (ULK) BEOL levels and also meet lead-free C4 EM requirements. FV design changes such as strategically offsetting a single or multiple FV vias towards the center of the chip and thus to the compressive side of the C4 bump has been shown to reduce the stresses in the ULK levels due to chip package interactions and hence significantly reduce the number of white bump fails. Changing the shape of the FV via to strategically distribute current more uniformly through the C4 bumps has also been shown to improve the C4 EM performance significantly, while lowering the overall stresses in the chip. Effects of final passivation thickness and via diameter on the white bump stresses will also be discussed. Supporting white-bump, C4 EM and electrical/mechanical modeling data showing the benefits of the design and integration changes will also be discussed in detail in the paper.