학술논문
A signal integrity enhancement technique for high speed test systems
Document Type
Conference
Author
Source
2011 24th Canadian Conference on Electrical and Computer Engineering(CCECE) Electrical and Computer Engineering (CCECE), 2011 24th Canadian Conference on. :001300-001303 May, 2011
Subject
Language
ISSN
0840-7789
Abstract
Signal integrity degradation at high frequencies affects test results and increases the yield loss of integrated circuits. Parasitic effects and electromagnetic coupling due to transmission lines degrade the integrity of test signals and undermine the accuracy of the measurement results. A new signal integrity enhancement technique is presented in this paper to compensate the signal loss. A Proportional-Integrator-Differentiator (PID) circuit is implemented as an overshoot generator to negate the undesired effects of transmission lines. Simulation results at 1GHz show that the proposed method can improve the rise and fall time by orders of magnitude, and increase the eye-opening by more than 40%.