학술논문
Efficient weighted modulo 2n+1 adders by partitioned parallel-prefix computation and enhanced circular carry generation
Document Type
Conference
Source
Proceedings of 2011 International Symposium on VLSI Design, Automation and Test VLSI Design, Automation and Test (VLSI-DAT), 2011 International Symposium on. :1-4 Apr, 2011
Subject
Language
Abstract
In this paper, we propose a low complexity design of weighted modulo 2 n +1 adder, derived by decomposition of parallel-prefix computation into several blocks of smaller input bit-widths. Besides, we have proposed a novel enhanced circular carry generation (ECCG) unit to process the carry-bits produced by all the parallel-prefix computation units (of small input bit-widths) to obtain the final modulo sum efficiently in terms of area-delay product. We have implemented the proposed adders using 0.13 μm CMOS technology; and from the synthesis results we find that our proposed adder outperforms the previously reported weighted modulo 2 n +1 adders. It offers a saving of area-delay product up to 49% over the existing methods.