부산대학교 도서관

BIST TPG (built in self test) for low power dissipation and high fault coverage presents a low hardware overhead test pattern generator (TPG) for scan-based built-in self-test (BIST) that can reduce switching activity in circuits under test (CUTs) during BIST and also achieve very high fault coverage with reasonable lengths of test sequences. The proposed BIST TPG decreases transitions that occur at scan inputs during scan shift operations and hence reduces switching activity in the CUT. The BIST TPG comprises of two TPG's, LT-RTPG and 3-weight WRBIST. Test patterns generated by the LT-RTPG detect easy-to-detect faults and test patterns generated by the 3-weight WRBIST detect faults that remain undetected after LT-RTPG patterns are applied. The BIST TPG does not require modification of mission logics, which can lead to performance degradation. Recently, techniques to reduce switching activity during BIST have been proposed. A straightforward solution is to reduce the speed of the test clock during scan shift operations. However, since most test application time of scan-based BIST is spent for scan shift operations, this will increase test application time by about a factor of if scan flip-flops are clocked at speed during scan shift operations. Larger reduction in switching activity is achieved in large circuits. Experimental results also show that the BIST-TPG can be implemented with low area overhead. Larger reduction in switching activity is achieved in large circuits. Experimental results also show that the BIST-TPG can be implemented with low area overhead