학술논문
A 1.6 GB/s data-rate 1 Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture
Document Type
Conference
Author
Source
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Solid-state circuits Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International. :376-377 1996
Subject
Language
ISSN
0193-6530
Abstract
This paper describes key technologies for a 1.6 GB/s high bandwidth 1 Gb synchronous DRAM (SDRAM). Its high data transfer rate and large memory capacity are intended for a unified memory system in which a single DRAM (array) is time-shared as both main memory and 3D graphics frame memory. 200 MHz operation is achieved by the hierarchical square-shaped memory block (SSMB) layout and the distributed bank (D-BANK) architecture. A built-in self-test (BIST) circuit with margin-test capability is included.