학술논문

Low-Complexity Policies for Energy-Performance Tradeoff in Chip-Multi-Processors
Document Type
Periodical
Source
IEEE Transactions on Very Large Scale Integration (VLSI) Systems IEEE Trans. VLSI Syst. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on. 16(9):1243-1248 Sep, 2008
Subject
Components, Circuits, Devices and Systems
Computing and Processing
Voltage control
Frequency
Energy efficiency
Energy consumption
Dynamic voltage scaling
Degradation
Computational complexity
Radio access networks
Very large scale integration
Battery charge measurement
Chip-multi-processor (CMP)
dynamic voltage scaling
low power
slack utilization
Language
ISSN
1063-8210
1557-9999
Abstract
Chip-multi-processor (CMP) utilize multiple energy-efficient processing elements (PEs) to deliver high performance while reducing energy-consumption. Dynamic frequency-Voltage Scaling (DVS) balances performance and energy consumption by varying PEs' frequency-voltage workpoints to save energy while meeting performance requirements. We consider multi-task CMP applications with unknown workloads, and dynamically set workpoints to minimize ${\rm ET}^{2}$ . Heuristic policies for serial/parallel task-graphs are investigated. We compare these policies to a theoretical bound and show that they achieve good results with low complexity. In most cases the simplest policy, which usually assigns constant workpoints, is also the most cost-effective one.