학술논문
A versatile low-jitter PLL in 90-nm CMOS for SerDes transmitter clocking
Document Type
Conference
Author
Source
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005. Custom Integrated Circuits Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005. :553-556 2005
Subject
Language
ISSN
0886-5930
2152-3630
2152-3630
Abstract
A low-jitter charge-pump PLL is built in 90-nm CMOS for 1-10 Gb/s SerDes transmitter clocking. The PLL employs a programmable dual-path loop filter with integrating path and novel resistorless proportional path that can be independently controlled and accurately modeled for flexible setting of closed-loop bandwidth and peaking. Frequency is synthesized using an area-efficient LC-VCO with helical inductors and inversion-mode nFET varactors for 45% tuning range. The PLL exhibits 0.81 ps rms jitter at 10.0 Gb/s. Technology considerations for improving design manufacturability, tuning range, and jitter performance are addressed.