학술논문
A hardware-accelerated framework with IP-blocks for application in MPEG-4
Document Type
Conference
Author
Source
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) System-on-Chip for Real-Time Applications System-on-Chip for Real-Time Applications, 2005. Proceedings. Fifth International Workshop on. :211-214 2005
Subject
Language
Abstract
In this paper we present a hardware-accelerated framework and hardware blocks for MPEG-4 part 10 IP-quality assessment. We give examples of various IP-blocks that have been designed and tested on the integration platform. The hardware-accelerated framework enabled us to asses their quality along with the MPEG-4 part 10 software reference model.