학술논문
Platform-based testbench generation
Document Type
Conference
Author
Source
2003 Design, Automation and Test in Europe Conference and Exhibition Design, automation and test in Europe Design, Automation and Test in Europe Conference and Exhibition, 2003. :1038-1043 2003
Subject
Language
ISSN
1530-1591
Abstract
This paper presents a new technology that accelerates system verification. In a real life example, we achieved a speed-up of a factor of about 5000. The key for this speed-up is a configurable, synthesizable testbench architecture, which can be completely mapped to emulators or FPGAs. Exploiting generic controllers and re-using protocol-specific stimuli generators combined with topology and microprogram generation is responsible for almost zero overhead compared to behavioral testbenches.