학술논문
A digital beamforming processor for multiple beam antennas
Document Type
Conference
Author
Source
International Symposium on Antennas and Propagation Society, Merging Technologies for the 90's Antennas and Propagation Society International Symposium, 1990. AP-S. Merging Technologies for the 90's. Digest.. :388-391 vol.1 1990
Subject
Language
Abstract
A generic digital beamformer architecture that has been implemented to demonstrate the advantages of digital beamforming is described. The digital beamforming processor has been implemented using quadratic residue number system techniques to enhance performance. The custom processor chips are implemented in 1.2- mu m CMOS technology. A digital beamformer can provide significantly better sidelobe performance than an RF beamformer. This is shown for a 64-channel system having only 8-bit weights (I and Q) and 9-bit signals (I and Q). Sidelobe levels can be suppressed 45 dB or better, Practical system implementation considerations are addressed.ETX