부산대학교 도서관

This paper addresses the electrical behavior of high-speed vertical interconnects for the assembly of high-performance computing (HPC) chiplets onto a PCB system board. These chiplets consist of a silicon interposer as carrier for multiple chips, e.g. high bandwidth memory (HBM) and ASICs. Through silicon vias (TSVs) are used to establish the required electrical connections from the top to the bottom of the interposer. The different aspects regarding the electrical performance of power and signal interconnects from the PCB to the fine pitch redistribution layer traces on the top side of the interposer are investigated based on 3D Full wave simulation results. The impact of using an equidistant TSV and BGA grid while maintaining design flexibility for routing of high-speed signals is discussed. All investigations are performed by taking potential disconnection-failures of TSVs into account to improve the stability and yield of such interposers.