부산대학교 도서관

In response to the evolving semiconductor landscape in light of Moore's law limitations, the industry has embraced System-in-Packages (SiPs) to increase functionality density, utilizing segregated dies called chiplets on a shared interposer substrate. However, procuring chiplets from uncertain sources and lacking supply chain visibility have heightened counterfeit vulnerabilities. This paper introduces Heterogeneous Integration Secure Split-Test (HI -SST), an approach to demonstrate how mitigating out-of-spec, defective, overproduced, and remarked chiplets and SiPs can be done through secure split testing. In HI -SST, we augment SiP architectures with two new trusted components, i.e., chiplet hardware security module (CHSM) and chiplet security IP (CSIP) within chiplets to streamline the communication of security assets as well as testing and authentication. Functional locking, testing data encryption, and a remarking detection mechanism are de-veloped within the CSIP to provide mitigation against the threats above. With a detailed security and performance evaluation, we also compare HI -SST with the conventional established SST and Connecticut-SST (CSST) solutions for monolithic ICs, showing how the foundation of such a solution requires a revisit in the domain of heterogeneous integration (HI).