학술논문

Impact of Back End of Line (BEOL) and Ambient Temperature on Self-Heating in Twin Nanowire Gate-All-Around FETs: Junctionless Mode Versus Inversion Mode
Document Type
Conference
Source
2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) Electron Devices Technology & Manufacturing Conference (EDTM), 2024 8th IEEE. :1-3 Mar, 2024
Subject
Bioengineering
Components, Circuits, Devices and Systems
Computing and Processing
Engineered Materials, Dielectrics and Plasmas
Engineering Profession
Fields, Waves and Electromagnetics
General Topics for Engineers
Photonics and Electrooptics
Performance evaluation
Three-dimensional displays
Thermal resistance
Field effect transistors
Gallium arsenide
Voltage
Logic gates
Nanowire GAA FETs
Self-heating effect
Junctionless mode
Inversion mode
Lattice temperature
Language
Abstract
Overall, the impact of BEOL effective thermal resistance $(\mathrm{R}_{\mathrm{T}\mathrm{H}})$ and isothermal ambient temperature $(\mathrm{T}_{\mathrm{A}})$ on the self-heating effect (SHE) in twin nanowire gate-all-around FETs, junctionless (JL) versus inversion mode (IM) are analyzed. The JL device performance is drastically improved by 5.1 % and 11.5 %, respectively, at higher $\mathrm{R}_{\mathrm{T}\mathrm{H}}$ and $\mathrm{T}_{\mathrm{A}}$. However, the IM device performance is traditionally degraded by ~7.4 % and 21.51 %, respectively, at higher $\mathrm{R}_{\mathrm{T}\mathrm{H}}$ and $\mathrm{T}_{\mathrm{A}}$.