학술논문

Development of Wide-JFET Trench-Etched Double-Diffused MOS (TED-MOS) for High-Voltage Applications
Document Type
Periodical
Source
IEEE Transactions on Electron Devices IEEE Trans. Electron Devices Electron Devices, IEEE Transactions on. 71(4):2570-2576 Apr, 2024
Subject
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
JFETs
Resistance
Electric fields
Silicon carbide
MOSFET
Logic gates
High-voltage techniques
33 kV
on-resistance
silicon carbide (SiC)
switching loss
trench MOSFET
Language
ISSN
0018-9383
1557-9646
Abstract
We developed a modified trench-etched double-diffused MOS (TED-MOS) suitable for high-voltage devices that can be designed with a wide JFET to suppress JFET resistance. Our evaluation of the static and dynamic characteristics of modified TED-MOS chips showed that, compared to 3.3-kV double-diffused MOS (DMOS) chips, a lower ${\textit R}_{\text {on}}{A}$ even with a higher ${V}_{\text {th}}$ could be achieved. We also proposed a method to evaluate the potential of the device structure from the viewpoint of gate surge voltage and showed that the gate surge voltage of TED-MOS is smaller than that of DMOS with the same ${\textit dv}/{\textit dt}$ , which we attribute to the smaller ${C}_{\text {rss}}/{C}_{\text {iss}}$ . This feature is particularly effective for silicon carbide (SiC) devices that suffer from TDDB.