부산대학교 도서관

A multilayer printed circuit board (PCB) design and measurement scenario corresponding to one of the high-speed interfaces is considered in this work. The design and measurement corresponding to HDMI 2.1 interface with fixed rate link (FRL) mode is reported, where each lane operates at 10Gbps with total bandwidth of 4lanes @10Gbps each for 4K (60/120Hz) performance. A full design of experiment (DoE) is carried out with IBIS-AMI model for Tx and specification-based Rx, connector & cable models, to comply with the requisite eye mask level for 1e-10 BER. The targeted eye mask level is analytically determined using the HDMI Compliance Test Specification (CTS). The simulated eye height and width are then compared with specification target (HFR1-7 Data Eye Mask Test) values. The fabricated board is also tested for HFR17 during the post silicon electrical validation (EV). It is observed that few of the samples has marginal eye mask violation that was not observed in the simulation. A step-by-step investigation is carried out to find the root cause with minimum false conditioning. The major findings associated with the test case measurements are discussed here to emphasize the possible source of degradation in eye margin leads to HFR1-7 test violation.