학술논문

Energy-Efficient FPGA Based Sleep Apnea Detection Using EEG Signals
Document Type
Periodical
Source
IEEE Access Access, IEEE. 12:40182-40195 2024
Subject
Aerospace
Bioengineering
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Engineered Materials, Dielectrics and Plasmas
Engineering Profession
Fields, Waves and Electromagnetics
General Topics for Engineers
Geoscience
Nuclear Engineering
Photonics and Electrooptics
Power, Energy and Industry Applications
Robotics and Control Systems
Signal Processing and Analysis
Transportation
Sleep apnea
Electroencephalography
Field programmable gate arrays
Feature extraction
Hardware
Support vector machines
Real-time systems
Inductive charging
Charge measurement
Vehicular ad hoc networks
Electric vehicle charging
Wireless charging
wireless power transfer
dynamic wireless charging
vehicle-to-vehicle wireless charging
electric vehicles charging
Language
ISSN
2169-3536
Abstract
Sleep apnea is a prevalent sleep disorder characterized by frequent interruptions in breathing during sleep, leading to decreased levels of blood oxygen. This research introduces an energy-efficient digital hardware system built on an Artix 7 FPGA, explicitly designed for real-time sleep apnea detection. Our approach involves the classification of subject-specific sleep apnea and non-apnea events. We utilize inter-band energy ratio features extracted from multi-band Electroencephalogram (EEG) signals and employ a Linear Support Vector Machine (LSVM) classifier for this task. The features extracted—namely energy, kurtosis, and mobility—from five sub-bands demonstrate improved accuracy, sensitivity, and specificity compared to existing studies. The proposed model is evaluated using EEG signals from the openly accessible St. Vincent’s sleep apnea UCDDB database. Our system achieves remarkable performance metrics, attaining the highest accuracy of 94.81%, a sensitivity of 93.10%, and a specificity of 96.43%. It accomplishes all this while maintaining minimal dynamic power consumption (19mW) and using minimal FPGA resources. This hardware system can be integrated into a System-on-a-Chip (SoC) platform, serving as a crucial component of a smart, wearable, automated sleep apnea detection device for real-time critical health diagnosis and screening.