학술논문
Unleashing Power Efficiency: A Study Comparing Pulsed Latches and Flip-Flops for Low-Power Applications
Document Type
Conference
Source
2023 3rd International Conference on Smart Generation Computing, Communication and Networking (SMART GENCON) Smart Generation Computing, Communication and Networking (SMART GENCON), 2023 3rd International Conference on. :1-7 Dec, 2023
Subject
Language
Abstract
This study conducts a comparative analysis of different pulsed latches and flip-flops in a low VDD region. Flip-flops are essential components in electronic circuits and have a noteworthy effect on circuit performance. They play a crucial function in digital systems, therefore minimizing their power consumption can significantly lower system power consumption. The study presents a comparative study of five flip-flop designs: TGFF, ACFF, TCFF, SC2FF, and SAFF, alongside pulsed latches, TGPL, and STPL, which address high t-setup issues. The Cadence Virtuoso tool in 90nm CMOS technology is used to implement each design.