학술논문
First Demonstration of Defect Elimination for Cryogenic Ge FinFET CMOS Inverter Showing Steep Subthreshold Slope by Using Ge-on-Insulator Structure
Document Type
Conference
Author
Yu, X.-R.; Hsieh, C.-C.; Chuang, M.-H.; Chiu, M.-Y.; Sun, T.-C.; Geng, W.-Z.; Chang, W.-H.; Shih, Y.-J.; Lu, W.-H.; Chang, W.-C.; Lin, Y.-C.; Pai, Y.-C.; Lai, C.-Y.; Dei, Y.; Yang, C.-Y.; Lu, H.-Y.; Lin, N.-C.; Wu, C.-T.; Kao, K.-H.; Ma, W. C.-Y.; Lu, D. D.; Lee, Y.-J.; Luo, G.-L.; Chiang, M.-H.; Maeda, T.; Wu, W.-F.; Li, Y.-M.; Hou, T.-H.
Source
2023 International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2023 International. :1-4 Dec, 2023
Subject
Language
ISSN
2156-017X
Abstract
This work presents experimental electrical characteristics and circuit prediction at cryogenic temperatures (down to 10 K) for three different kinds of germanium (Ge)-based FETs with advanced Fin/GAA structures. Among them, the layer transferred Ge-on-Insulator (GeOI) FinFET significantly improves its I-V characteristic during cryogenic measurements, such as a steeper subthreshold swing at 10K and a better I on . The developed GeOI fabrication method provides an effective way to eliminate the defects originating from misfit dislocations at the Ge/Si substrate during epitaxial growth, which would be treated as the key to device performance enhancement under 10 K. According to the measured IV at 10 K and circuit prediction, GeOI FinFETs with high Ge crystallinity are strong candidates for High-Performance-Computing (HPC) applications.