학술논문
Design of Analog-AI Hardware Accelerators for Transformer-based Language Models (Invited)
Document Type
Conference
Author
Burr, G. W.; Tsai, H.; Simon, W.; Boybat, I.; Ambrogio, S.; Ho, C.-E.; Liou, Z.-W.; Rasch, M.; Buchel, J.; Narayanan, P.; Gordon, T.; Jain, S.; Levin, T. M.; Hosokawa, K.; Le Gallo, M.; Smith, H.; Ishii, M.; Kohda, Y.; Chen, A.; Mackin, C.; Fasoli, A.; ElMaghraoui, K.; Muralidhar, R.; Okazaki, A.; Chen, C. -T.; Frank, M. M.; Lammie, C.; Vasilopoulos, A.; Friz, A. M.; Luquin, J.; Teehan, S.; Ahsan, I.; Sebastian, A.; Narayanan, V.
Source
2023 International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2023 International. :1-4 Dec, 2023
Subject
Language
ISSN
2156-017X
Abstract
Analog Non-Volatile Memory-based accelerators offer high-throughput and energy-efficient Multiply-Accumulate operations for the large Fully-Connected layers that dominate Transformer-based Large Language Models. We describe architectural, wafer-scale testing, chip-demo, and hardware-aware training efforts towards such accelerators, and quantify the unique raw-throughput and latency benefits of Fully-(rather than Partially-) Weight-Stationary systems.