학술논문

3D Stacked Devices and MOL Innovations for Post-Nanosheet CMOS Scaling

Document Type

Conference

Author

Horiguchi, N.; Mertens, H.; Chiarella, T.; Demuynck, S.; Vega-Gonzalez, V.; Vandooren, A.; Veloso, A.; Bardon, M. Garcia; Sisto, G.; Gupta, A.; Tokei, Z.; Biesemans, S.; Ryckaert, J.

Source

2023 International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2023 International. :1-4 Dec, 2023

Subject

Bioengineering
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Engineered Materials, Dielectrics and Plasmas
Fields, Waves and Electromagnetics
Nuclear Engineering
Photonics and Electrooptics
Power, Energy and Industry Applications
Robotics and Control Systems
Signal Processing and Analysis
Performance evaluation
Technological innovation
Three-dimensional displays
Computer architecture
Routing
Nanoscale devices
Business process re-engineering

Language

ISSN

2156-017X

Abstract

3D stacked devices without area penalty from device-device space, such as complementary FET (CFET), is promising for post-nanosheet CMOS scaling. New MOL architectures, such as backside power delivery network (BSPDN) or Vertical-Horizontal-Vertical routing style, are required to connect 3D stacked devices without wiring congestions and resistance increase. Process/material innovations are necessary to enable high aspect ratio and 3D integration in CFET integration with new MOL architectures.

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