학술논문
DrGaN: an Integrated CMOS Driver-GaN Power Switch Technology on 300mm GaN-on-Si with E-mode GaN MOSHEMT and 3D Monolithic Si PMOS
Document Type
Conference
Author
Then, Han Wui; Radosavljevic, M.; Bader, S.; Zubair, A.; Vora, H.; Nair, N.; Koirala, P.; Beumer, M.; Nordeen, P.; Vyatskikh, A.; Hoff, T.; Peck, J.; Nahm, R.; Michaelos, T.; Khora, E.; Jordan, R.; Hoffman, C.; Franco, N.; Oni, A.; Beach, S.; Garg, D.; Frolov, D.; Latorre-Rey, A.; Mitaenko, A.; Rangaswamy, J.; Sarkar, S.; Ahmed, S.; Rayappa, V.; Chiu, H.; Hubert, A.; Brophy, S.; Arefm, N.; Desai, N.; Krishnamurthy, H.; Yu, J.; Ravichandran, K.; Fischer, P.
Source
2023 International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2023 International. :1-4 Dec, 2023
Subject
Language
ISSN
2156-017X
Abstract
We demonstrate industry’s first CMOS "DrGaN" technology fabricated in a 300mm GaN-on-Silicon process combining enhancement-mode high-k dielectric GaN MOSHEMT with integrated 3D monolithic Si PMOS by layer transfer. The 180nm DrGaN with power transistor width of 421.1mm achieves an excellent R ON = ImΩ (R DSON =0.8 mfl-mm 2 ) and drain leakage well below 0.1mA. In this work, we demonstrate a truly gate-last 3D monolithic integration process, where the high temperature activation steps for the Si PMOS transistors are completed before the gate dielectric of the GaN MOSHEMT transistors is deposited. This resolves one major hurdle in the 3D monolithic integration of GaN and Si CMOS transistors. Moreover, in this new process, the GaN and Si CMOS transistors share the same backend interconnect stack for reduced mask count and no additional intra-connects. The best FOM=1/(R ON Q GG ) of 0.59 (mΩ-nC) -1 is achieved for a L G 30nm GaN MOSHEMT.