학술논문

Developing a Monolithic Silicon Sensor in a 65nm CMOS Imaging Technology for Future Lepton Collider Vertex Detectors
Document Type
Conference
Source
2022 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC) Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2022 IEEE. :1-7 Nov, 2022
Subject
Components, Circuits, Devices and Systems
Computing and Processing
Engineered Materials, Dielectrics and Plasmas
Nuclear Engineering
Photonics and Electrooptics
Signal Processing and Analysis
Monte Carlo methods
Prototypes
Detectors
Sensor phenomena and characterization
CMOS technology
Semiconductor process modeling
Research and development
Language
ISSN
2577-0829
Abstract
Monolithic CMOS sensors in a 65nm imaging technology are being investigated by the CERN EP Strategic R&D Programme on Technologies for Future Experiments for an application in particle physics. The appeal of monolithic detectors lies in the fact that both sensor volume and readout electronics are integrated in the same silicon wafer, providing a reduction in production effort, costs and scattering material. The Tangerine Project WP1 at DESY participates in the Strategic R&D Programme and is focused on the development of a monolithic active pixel sensor with a time and spatial resolution compatible with the requirements for a future lepton collider vertex detector. By fulfilling these requirements, the Tangerine detector is suitable as well to be used as telescope planes for the DESY-II Test Beam facility. The project comprises all aspects of sensor development, from the electronics engineering and the sensor design using simulations, to laboratory and test beam investigations of prototypes. Generic TCAD Device and Monte-Carlo simulations are used to establish an understanding of the technology and provide important insight into performance parameters of the sensor. Testing prototypes in laboratory and test beam facilities allows for the characterization of their response to different conditions. By combining results from all these studies it is possible to optimize the sensor layout. This contribution presents results from generic TCAD and Monte-Carlo simulations, and measurements performed with test chips of the first sensor submission.