학술논문
A TDC With Integrated Snapshot Circuit and Calibration in 28-nm CMOS
Document Type
Periodical
Author
Source
IEEE Transactions on Circuits and Systems II: Express Briefs IEEE Trans. Circuits Syst. II Circuits and Systems II: Express Briefs, IEEE Transactions on. 71(3):1581-1585 Mar, 2024
Subject
Language
ISSN
1549-7747
1558-3791
1558-3791
Abstract
This brief presents a 135ps dynamic range, 5.45ps effective resolution 2D Vernier time-to-digital converter for use in an all-digital phase-locked-loop. The matrix readout array limits the number of delay cells necessary by using all taps of the delay lines. A full calibration scheme is presented. It calibrates the system against PVT variations and maintains and favors a linear operation over achieving a specified resolution. The proposed architecture is fabricated in a 28nm CMOS technology and consumes 360 $\pmb {\mu }\text{W}$ at 0.9V supply voltage and 55MS/s conversion rate.