학술논문

Satisfiability Attack-Resilient Camouflaged Multiple Multivariable Logic-in-Memory Exploiting 3D NAND Flash Array
Document Type
Periodical
Source
IEEE Transactions on Circuits and Systems I: Regular Papers IEEE Trans. Circuits Syst. I Circuits and Systems I: Regular Papers, IEEE Transactions on. 71(2):660-669 Feb, 2024
Subject
Components, Circuits, Devices and Systems
Three-dimensional displays
Logic gates
Flash memories
Threshold voltage
Logic arrays
Integrated circuits
Logic functions
3D NAND flash
logic-in-memory
reverse engineering
IC camouflaging
SAT attack
Language
ISSN
1549-8328
1558-0806
Abstract
Logic-in-memory implementations have attracted significant attention recently for energy efficient in-situ processing of big data in this era of IoT. However, the emerging memory technologies such as RRAMs, PCMs, STT-MRAMs, etc. are still immature and exhibit significant spatial and temporal variations limiting the yield and the size of crossbar arrays available for implementing logic functions. Considering the technological maturity, ultra-high density and ultra-low cost of 3D NAND flash memory, in this work, we have proposed a novel methodology to exploit 3D NAND flash memory for realizing any logic function in sum-of-product form (SOP) with ≤177 literals/inputs and $\le 2^{14}$ minterms parallelly. Moreover, all the logic functions realized using the proposed technique appear same at the layout level rendering the logic-in-memory implementation utilizing the 3D NAND flash memory an innate camouflaging property and an inherent immunity against security vulnerabilities in the semiconductor supply chain. We have also evaluated the resiliency of the proposed technique against reverse engineering attacks such as SAT attacks, ATPG attacks and brute force attacks on ISCAS’85 and ISCAS’89 benchmark circuits. Our results indicate that the proposed logic-in-memory implementation facilitates complete obfuscation of the logic function without introducing any area overhead and exhibits a strong resiliency against reverse engineering.