부산대학교 도서관

This article presents a novel ultrawideband chip-to-chip interconnect that uses bond wire with sidewalls to address the limitations of conventional bond-wire interconnects. These limitations include reduced bandwidth due to parasitic components and potential performance degradation caused by dielectric resonance in the silicon substrate. To overcome these limitations, the proposed technique utilizes metallic sidewalls around the bond wire, formed by bumps on a septum, to serve as a ground and compensate for parasitic inductance. Additionally, the characteristic impedance of bond wire is adjusted and matched to the reference by encapsulating the overall structure with molding epoxy, which also functions as interconnect protection. A metallic septum isolates two silicon chips electromagnetically and removes dielectric resonances from the frequency range of near dc to 170 GHz. To validate the effectiveness of the proposed technique, two silicon CMOS chips consisting of 50- $\Omega $ microstrip lines were interconnected using the conventional and proposed bond-wire interconnects. The on-wafer measurements demonstrated a significant improvement of the proposed interconnects in insertion and return losses for chip spacings of both 200 and $500~\mu \text{m}$ . Specifically, for a chip spacing of $500~\mu \text{m}$ , the overall structure using the proposed interconnect exhibited an average insertion loss of 3.7 dB across the range of $D$ -band (110–170 GHz), which is 5.0 dB lower than the conventional bond-wire interconnect. Return loss was better than 13.4 dB across a range from near dc to 170 GHz. The proposed wire interconnects exhibited a net loss of less than 2.0 dB up to 170 GHz, estimated by subtracting the measured loss of microstrip lines on the CMOS chips. To the best of our knowledge, this is the first demonstration of a silicon chip-to-chip interconnect using bond wire with a 3-dB bandwidth greater than 170 GHz.