부산대학교 도서관

STT-MRAM is a promising candidate to replace SRAM in Last Level Caches (LLCs) thanks to its high density and reduced leakage. However, write delay, write energy, defects and risk of breakdown have hindered its widespread adoption. To address these challenges, the bitcell and bias conditions need to be co-optimized. We present a Design Technology Co-optimization (DTCO) strategy for LLC eSTT-MRAM based on a new defects-aware stochastic framework, calibrated on an experimental MTJ array and applied to 5 nm and 3 nm nodes FinFET core devices. With an area equivalent to 32% of an SRAM bitcell, the optimized STT-MRAM bitcell achieves 15 ns and 1.1/1.4 pJ per write.