부산대학교 도서관

This brief proposes a nano-watt self-biased CMOS voltage reference (SBCVR) with a quasi self-cascode current mirror (QSCCM) for better line sensitivity (LS) and power supply rejection ratio (PSRR). A self-cascode MOSFET (SCM) and a cascode structure are combined as the QSCCM to reduce the variations of bias current $(I_{\mathrm{ B}})$ through the QSCCM, comparing to conventional ones. Then, the $I_{\mathrm{ B}}$ is fed into an active load to acquire a more stable reference voltage $(V_{\mathrm{ REF}})$ against the supply voltage $(V_{\mathrm{ DD}})$ without using any additional native devices, amplifiers, pre-regulation circuits, and DIBL compensation circuits. The proposed SBCVR with the QSCCM is fabricated in a standard $0.18 \mu \text{m}$ CMOS process, while 22 chip samples are measured. The results show that the average LS is 0.011%/V when the $V_{\mathrm{ DD}}$ varies from 0.8 V to 1.8 V. The average PSRR are −76dB, −53 dB, and −59 dB at 10Hz, 1kHz, and 1MHz respectively. Moreover, it can produce a $V_{\mathrm{ REF}}$ of 293 mV and consume a supply current of 1.95 nA $(V_{\mathrm{ DD}}=$ 1V) at 27 °C. The average temperature coefficient (TC) is 66.1 ppm/°C without trimming in the temperature range from −40 °C to 85 °C, while the total area is only 0.004 mm 2.