부산대학교 도서관

In high-speed serializer/deserializer (SerDes) channels, reducing impedance mismatches at the differential via is crucial to minimize signal reflection. However, due to the complex 3-D structure of the differential via, obtaining optimal design parameters for impedance matching can be a time-consuming process. This article introduces an equation-based time-domain reflectometry (TDR) estimation model for the differential via, which is validated by comparing it with a commercial model of the coupled transmission line. In addition, this article proposes a method to optimize the design parameters of the differential via using a figure of merit (FOM) based on TDR impedance in a particle swarm optimization (PSO) algorithm. The optimization procedure is applied to an actual printed circuit board (PCB) design, and the simulation results, including TDR, ${S}$ -parameters, and bit error rate (BER) at 1E −12 contours, validate the optimization performance. To further verify the optimization performance in a realistic scenario, test coupons are fabricated, and the TDR impedance is measured, demonstrating excellent performance in real-world conditions.