학술논문

Subtractive Photonics in Bulk CMOS
Document Type
Periodical
Source
IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 58(11):3030-3043 Nov, 2023
Subject
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Computing and Processing
Photonics
Optical waveguides
Geometry
Metals
Loss measurement
Optical losses
Ribs
CMOS
optoelectronics
photonics
waveguides
Language
ISSN
0018-9200
1558-173X
Abstract
Subtractive photonics is presented as a method for implementing photonic waveguides into any bulk CMOS or electronics process. Metal and glass are patterned in the backend layers by the foundry to reveal suspended dielectric waveguides when the metal is etched away. This method requires a simple wet etch and provides waveguiding of light up to the visible regime using the broad transparency windows of silicon oxides. Mechanical, chemical, and photonic considerations are discussed, and photonic design is extensively detailed in the context of a 180-nm CMOS process. Example waveguides are constructed and measured, with losses as low as 4.1 dB/cm for a multimode waveguide at 1550 nm. In addition, waveguides are measured in the visible range, waveguide-photodiode couplers are detailed, and electronic–photonic systems are demonstrated to be unaffected by the etching.