학술논문

On the Unpredictability of SPICE Simulations for Side-Channel Leakage Verification of Masked Cryptographic Circuits
Document Type
Conference
Source
2023 60th ACM/IEEE Design Automation Conference (DAC) Design Automation Conference (DAC), 2023 60th ACM/IEEE. :1-6 Jul, 2023
Subject
Components, Circuits, Devices and Systems
Computing and Processing
Engineering Profession
Design automation
Layout
SPICE
Hardware
Timing
Cryptography
side-channel attack
transistor-level simulation
masking scheme
domain-oriented masking
Language
Abstract
Circuits for cryptography are vulnerable to side-channel (SC) attacks. Masking is a countermeasure which splits secrets into random shares. It is provable secure under the assumption that physical leakage of each share is independent of each other. For a secure implementation of masked circuits, this independency assumption must be satisfied after layout. A transistor-level simulator such as SPICE produces analog waveforms that are sufficiently trustworthy to verify timing accuracy. Due to this accuracy, SPICE is expected to be useful for SC leakage verification after layout. However, we demonstrate that the statistical variation of the power noise amplitude in SPICE simulation is not always correct and varies a lot for SC evaluation. We believe it results from the internal time-step creation optimized for efficiency. It causes false-positives in the verification of security order. A small nonlinear function with a domain-oriented masking scheme is used to demonstrate these SPICE-simulation anomalies.