부산대학교 도서관

A new SPICE model for vertical nand (VNAND) flash memory cells is proposed based on the BSIM-CMG model and a modified mobility equation using the Meyer-Neldel (MN) rule. Unlike in previous models, the average and standard deviation of the subthreshold swing (SS), threshold voltage ( ${V}_{\text {th}}$ ), maximum transconductance ( ${g}_{\text {m,max}}$ ), maximum word-line (WL) voltage ( ${V}_{\text {WL,max}}$ ), and maximum bitline (BL) current ( ${I}_{\text {max}}$ ) of WL cells at various positions are accurately modeled over the full BL/WL bias range. The step response in transient SPICE simulation agrees very well with a calibrated Technology Computer Aided Design (TCAD) model. Also, a new compact model that predicts ${V}_{\text {th}}$ change during program/erase (PGM/ERS) operation is proposed and validated. The model is expected to be beneficial for analog applications, such as synaptic devices in neural networks.