학술논문

A Novel Thermal-Aware Floorplanning and TSV Assignment With Game Theory for Fixed-Outline 3-D ICs
Document Type
Periodical
Source
IEEE Transactions on Very Large Scale Integration (VLSI) Systems IEEE Trans. VLSI Syst. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on. 31(11):1639-1652 Nov, 2023
Subject
Components, Circuits, Devices and Systems
Computing and Processing
Through-silicon vias
Integrated circuits
Game theory
Clustering algorithms
Silicon
Rapid thermal processing
Power distribution
Deep k-means clustering
game theory
thermal-aware floorplanning
three-dimensional integrated circuits (3-D ICs)
through silicon vias (TSVs)
Language
ISSN
1063-8210
1557-9999
Abstract
High temperature or temperature nonuniformity has been considered as one of the most challenging problems in three-dimensional integrated circuits (3-D ICs). There have been many studies on the thermal issues in 3-D ICs floorplanning. However, most handcrafted heuristic algorithms require long iteration cycles, resulting in inefficient thermal management with no guarantee of good performance. Meanwhile, as modern integrated circuit design becomes increasingly complex, current floorplannings suffer from the “curse of dimensionality” and cannot optimize large-scale cases. Therefore, a novel thermal-aware fixed-outline 3-D IC floorplanning is proposed in this article. Since the temperature in a 3-D IC is mainly determined by a power distribution across tiers, this article proposes a deep ${k}$ -means clustering algorithm to cluster the modules and find a better cross-tier power distribution. This is an unsupervised machine-learning algorithm that can successfully cluster high-dimensional sample data. Then, in the global distribution (GD) stage, we not only consider the power consumption between the groups but also apply the number and area of through silicon vias (TSVs) to the clustering and analytical method in the multilevel framework. Inspired by the fact that finding the optimal TSV positions for multiple nets in the TSV assignment (TA) stage is essentially a way to maximize the benefits of nets in a competitive environment, game theory is applied to further reduce temperature and wirelength in this stage. We prove that it is an ordinal potential game, and then converge to the Nash equilibrium by the best response strategy. Experimental results demonstrate that the proposed method shows good performance in reducing the temperature of 3-D ICs, and its running time is quite fast.