학술논문
A Memory Based Concurrence Detector for SPAD ToF Image Sensors
Document Type
Conference
Author
Source
2023 International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC) Circuits/Systems, Computers, and Communications (ITC-CSCC), 2023 International Technical Conference on. :1-5 Jun, 2023
Subject
Language
Abstract
This work presents an area efficient memory based concurrence detector (MCD) for Time-of-flight (ToF) image sensors. The proposed MCD consists of four 10-bit registers, register selector and a coarse bit comparator. 4 × 4 pixel array of MCD based single-photon avalanche diode (SPAD) histogramming circuit is implemented in 0.18 μm CMOS process with an area of 970μm X 124 μm, 59% less area compared to the conventional 4-pixel concurrence detector(CD) based SPAD histogramming circuit. Peak to background ratio and peak count rate are improved by X 0.13 and X 2.4 respectively, compared to the conventional 4-pixel CD based SPAD histogramming circuit.