부산대학교 도서관

Hardware implementation of elliptic curve cryptography (ECC) is a more competent operation in the field of cryptosecurity. Area, time, and power consumption are contradictory parameters for ECC processors. One of these parameters needs to be sacrificed to achieve effectiveness in terms of others. This research presents a 256-bit modified interleaved modular multiplication (IMM) over the prime field that uses fewer area slices and runs faster. Our main goal is to design a modular multiplier by minimizing the required area and keeping frequency maximum with less power consumption. The hardware architecture is developed with the help of the modified IMM algorithm. The hardware implementations are carried out using Xilinx software on Kintex-7 and Virtex-5 field programmable gate array (FPGA) technology. The suggested modular multiplier achieves a computation time of approximately 1.90108 μs at a maximum frequency of 134.660 MHz in Kintex-7 and 2.09176 μs at a maximum frequency of 77.9157 MHz in Virtex-5. We have preferred a 256-bit prime field among other prime fields for the Koblitz curve ECC. Almost no (0%) slice registers and just 3% of slice lookup tables (LUTs) are used in the proposed architecture. To obtain the simulation results, Modelsim software is utilized, and for verification purposes, Maple software is employed in this case. The modified algorithm suggests a more area and time-efficient hardware architecture that provides a higher throughput rate and less area-time product for elliptic curve cryptographic processors (ECP).