학술논문
A Compact Front-End Circuit for a Monolithic Sensor in a 65-nm CMOS Imaging Technology
Document Type
Periodical
Author
Piro, F.; Rinella, G.A.; Andronic, A.; Antonelli, M.; Aresti, M.; Baccomi, R.; Becht, P.; Beole, S.; Braach, J.; Buckland, M.D.; Buschmann, E.; Camerini, P.; Carnesecchi, F.; Cecconi, L.; Charbon, E.; Contin, G.; Dannheim, D.; de Melo, J.; Deng, W.; di Mauro, A.; Vassilev, M.D.; Emiliani, S.; Hasenbichler, J.; Hillemanns, H.; Hong, G.H.; Isakov, A.; Junique, A.; Kluge, A.; Kotliarov, A.; Krizek, F.; Kugathasan, T.; Lautner, L.; Lemoine, C.; Mager, M.; Marras, D.; Martinengo, P.; Masciocchi, S.; Menzel, M.W.; Munker, M.; Rachevski, A.; Rebane, K.; Reidt, F.; Russo, R.; Sanna, I.; Sarritzu, V.; Senyukov, S.; Snoeys, W.; Sonneveld, J.; Suljic, M.; Svihra, P.; Tiltmann, N.; Usai, G.; van Beelen, J.B.; Vernieri, C.; Villani, A.
Source
IEEE Transactions on Nuclear Science IEEE Trans. Nucl. Sci. Nuclear Science, IEEE Transactions on. 70(9):2191-2200 Sep, 2023
Subject
Language
ISSN
0018-9499
1558-1578
1558-1578
Abstract
This article presents the design of a front-end circuit for monolithic active pixel sensors (MAPSs). The circuit operates with a sensor featuring a small, low-capacitance (< 2 fF) collection electrode and is integrated into the DPTS chip, a proof-of-principle prototype of $1.5\times1.5$ mm including a matrix of $32\times32$ pixels with a pitch of $15 \mu \text{m}$ . The chip is implemented in the 65-nm imaging technology from the Tower Partners Semiconductor Company foundry and was developed in the framework of the EP-Research and Development Program at CERN to explore this technology for particle detection. The front-end circuit has an area of $42 \mu \text{m}^{2}$ and can operate with power consumption as low as 12 nW. Measurements on the prototype relevant to the front end will be shown to support its design.